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The prior art in memory systems includes integrated circuit, core, bubble, CCD, and other types of memory systems. The most pertinent prior art is integrated circuit RAM systems.
The prior art provides RAMs having tristate control for memory data lines to permit bussing of memory data lines and to facilitate bi-directional communication to the RAM for reading and writing of information from the bus. The most pertinent prior art in memory systems is discussed in the parent applications related to memories and is represented by the art cited herein.
The present invention is generally directed to improved memory architecture for multitudes of applications, such as providing greater performance and economy of implementation. In one memory configuration, a speed improvement is obtained by a combination of addressing the memory at a relatively low rate and scanning information out of the memory at a relatively high rate. This may be characterized as a multi-dimensional memory architecture, where the addressing logic forms a first dimension and the scanout logic forms a second dimension.
This speed improvement can be implemented by using the memory tristate control logic for data scanout operations in conjunction with addressing logic to provide both, re-addressing and scanout of memory data. A still further feature of the present invention provides an improved filter processor for a display system. Yet another feature of the present invention provides an improved performance memory arrangement.
The foregoing and other objects, features, and advantages of the present invention will become apparent from the following detailed description of preferred embodiments of this invention as illustrated in the accompanied drawings. A better understanding of the present invention may be obtained from a consideration of the detailed description hereinafter taken in conjunction with the drawings, which are briefly described below.
To facilitate disclosure of the illustrated embodiments, the components shown in FIGS. The components in the figures have in general been assigned reference numerals, where the hundreds digit of each reference numeral corresponds to the figure number. For example, the components in FIG.
A graphics processor architecture can be implemented with a address generator and control logic generating graphics vectors for storing into image memory. Image memory can then be scanned out, such as in a raster scan form to refresh a display. In one configuration, graphics vectors can be written into image memory on an offline basis and can be used to refresh the display on an online basis.
Alternately, graphics vectors can be written into image memory on an online basis time shared with refreshing of the display on an online basis. One arrangement of the graphics system of the present invention is shown in FIG. Supervisory processor A loads graphics commands into address generators B. Address generators B generate addresses of graphics vectors for loading into image memory C and for raster scanning image memory C.
An experimental system has been constructed to demonstrate operation of the graphics display capability. The arrangement shown in FIG. ASC, can be used to control that experimental hardware for refreshing the display. In this experimental system, the graphics vectors are loaded in an offline manner with the LD. ASC herein; emulating hardware loading of graphics vectors in an online manner.
In this experimental system, graphics operation is initiated each frame with supervisory processor A and hardware refresh is performed with address generators B and image memory C. In a hardware configuration, graphics vector generation can be performed in real time using the software emulated vector generation capability implemented in hardware form. In one hardware configuration, graphic vectors can be generated cotemporaneously with refresh, such as with one set of address generators i.
In this configuration, image memory can be implemented as a dual-ported image memory for simultaneously loading vectors into image memory and scanning-out image memory. In an alternate hardware configuration, graphic vectors can be generated and loaded into image memory during the vertical sync pulse period when the raster scan is blanked; time sharing the logic and memory between raster scanout and graphics generation.
In this configuration, during the vertical sync period, the address generators can generate graphic vector addresses for loading the graphic vectors into image memory and, after the vertical sync period, the address generators can generate the raster scan addresses for scanning-out image memory for display. The address generators can be used to generate graphic vectors and windows. For example, the LD. ASC herein has been used to load graphic vectors into image memory.
This is achieved by using the address generators to generate the addresses of a vector and by strobing the color intensity of the vector into image memory. Periods of time exist when the address generators are in a stand-by condition. For example, in a configuration where the address generators are scanning-out image memory to refresh a display; the address generators may not be used during the vertical blanking period and therefore may be available for graphic generation.
Also, in a configuration where the address generators are not used during the horizontal blanking period, the address generators and therefore may be available for graphic generation during the horizontal blanking period.
For example, a vertical blanking period of 1-millisecond will permit the address generators to draw about 5,graphic vector pixels operating at a 5-MHz pixel rate. Consequently, a meaningful number of graphic vector pixels can be generated during standby periods, permitting time sharing of the address generators for both, scanning-out an image to refresh a display and graphic vector generation.
A vector memory can be implemented to store parameters associated with the vectors to be generated. Vector memory can be loaded from various sources, such as from the supervisory processor that initializes the address generators, from a host processor, or from other sources.
The vector memory can contain the start point coordinates and the vector deltas for the address generators and a quantity Parameter or distance-to-go DTG parameter related to the quantity of vector steps to be generated for the particular vector. During image processing standby periods, graphic vector parameters can be loaded from the vector memory for generating the vectors with the address generators, similar to that performed with the LD. ASC program. After various standby periods, such as the horizontal and vertical synchronization periods; the address generators can be reinitialized; thereby overcoming the need to buffer scanout parameters.
However, if the address generators will not be reinitalized following vector generation, it may be necessary to buffer the scanout address parameters in a buffer memory for reloading the pixel address generators after vector generation. In the LD. ASC program, the number of steps for a vector are counted under program control in the supervisory processor. In a hardwired implementation, the number of steps for a vector can be counted with a hardware counter circuit.
For example, the quantity or DTG parameter from the vector memory can be loaded into a 74LS counter as a parallel load parameter and the counter can be decremented in the count-down mode for each pixel step during vector generation. Generation of the vector can be terminated by detecting the underflow signal from the counter at the zero count. Loading of the address generators from the vector memory can be performed in a manner similar to loading the address generators from the supervisory processor, as shown in the LD.
ASC program listing herein and as discussed relative to the supervisory processor interface herein. Setting of the vector color intensity from the vector memory can be performed in a manner similar to setting of the vector color intensity from the supervisory processor in the LD. Selecting of the write-mode for the image memory can be performed in a manner similar to setting of the write-mode with the load command signal DOA6 by the supervisory processor in the LD.
Window generation can be implemented with parameters for a plurality of images stored in a window buffer memory and selected as the address generators scan across window boundaries during scanout and refresh of the CRT monitor. When the address generators cross window boundaries, the previous display parameters can be buffered in the buffer memory and the display parameters associated with the new image can be loaded from the window buffer memory into the address generators.
Loading of display parameters associated with the new image from the window buffer memory can be accomplished as discussed above for loading of vector parameters during graphic vector generation.
Storing of display parameters associated with the prior image into the window buffer memory can be accomplished by reversing the vector generation loading operation to obtain a window generation store operation. Display systems can be implemented with spatial filters for anti-aliasing, pattern recognition, enhancement, and other purposes.
A spatial filter arrangement will now be discussed with reference to FIGS. Address generator A generates pixel addresses to access a plurality of pixels, such as a 9-pixel kernel H, from image memory B. ASC herein. Weight table C supplies a plurality of kernel weights appropriate to spatial filtering of the pixel kernel, such as a kernel of 9-weights I, from weight table C. The pixel intensities I0 to I8 are each applied to a corresponding multiplier E and the weights W0 to W8 are each applied to a corresponding multiplier E for multiplying the corresponding intensity and weight together to generate product signals J.
Product signals J are summed together with summer F to generated a weighted and mixed pixel intensity, which is converted to analog signal form with DAC G to excite a CRT display.
The arrangement discussed with reference to FIG. Intensity information INT and weight information WT can be input to multipliers A for weighting the pixel intensities, which in turn can be input to adders B and D for generating weighted and summed signal D.
Three channels of the arrangement discussed with reference to FIG. For example, as shown in FIG. The sum-of-the-products processing discussed above can be implemented with commercially available integrated circuit components, such as multiplier chips and adder chips.
For example, multiplier chips are manufactured by TRW and adder chips are manufactured by Texas Instruments. The memory architecture of the present invention has important advantages in implementing digital systems. It is applicable to special purpose systems; such as display systems, array processors, and pipeline processors; and is applicable to general purpose systems; such as general purpose digital computers.
It incorporates various features that may be used individually or in combinations to enhance performance and efficiency. One feature provides for accessing of memory at a relatively slow addressing rate and at a relatively fast scanout rate. Another feature provides a buffer memory to permit accessing of memory at a lower rate and higher duty cycle for information that is utilized at a higher rate and lower duty cycle.
Various other features are also discussed herein. Memory speed is an important consideration for design of digital systems; such as display systems, array processing systems, and pipeline systems.
A configuration is discussed herein where system speed can be implemented to be significantly faster than implied by memory speed considerations. This configuration uses a combination of novel architectural features for outputting of relatively high bandwidth information with a relatively low bandwidth memory. Memory arrangements have previously been disclosed in the related patent applications referenced herein in accordance with the present invention; such as implementing re-addressing and scanout operations to enhance memory capabilities.
Various embodiments were disclosed; including filter configurations, display configurations, and general purpose computer configurations. Now, filter configurations; display configurations; and general purpose computer configurations, including microcomputer and microprocessor configurations will be further disclosed. Also, other configurations; such as television, array processor, signal processor, cache memory, artificial intelligence, and DMA configurations; will be disclosed.
These disclosures are intended to be illustrative of other configurations; such as other special purpose computer configurations and other general purpose computer configurations. Display, signal processing, and filter processing configurations may be considered to be special purpose computer configurations. Also; filter processors, speech processors, signal processors, and display processors may be considered to be array processors.
Also; filter processors and speech processors may be considered to be signal processors. Further; filter processors include correlation processors, Fourier transform processors, recursive filter processors, and others.
Nevertheless, the teachings herein are generally applicable to processor systems and memory systems and are not limited to the specific applications disclosed herein. The terms computer and processor may be used interchangeably herein.
Some of the features of the present invention may be characterized as adaptive memory control, closed loop memory control, and memory servo control. For example, the memory may be considered to adaptively adjust to address characteristics. Also, the memory system may be considered to be in a closed loop or a servo loop by controlling address generation in response to the generated address. In one configuration; a detector detects a characteristic of the address, such as a change in the address MSBs, and invokes a time delay to delay generation of the next address in response thereto.
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