Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising. If you continue browsing the site, you agree to the use of cookies on this website. See our User Agreement and Privacy Policy. See our Privacy Policy and User Agreement for details. Published on May 23,

Author:Galkree Tarn
Language:English (Spanish)
Published (Last):20 September 2011
PDF File Size:16.87 Mb
ePub File Size:12.67 Mb
Price:Free* [*Free Regsitration Required]

Ref document number : Country of ref document : DE. Date of ref document : Ref country code : GB. Payment date : Year of fee payment : Ref country code : NL. Ref country code : DE. Effective date : In digital logic systems, one may have to compare the phases of two separate pulse trains in order to extract information.

This information is therefore more or less encoded in the two pulse trains by the "Time overlap" of certain pulses, that is to say, the coincidence in time of at least a portion of a pulse of a first set for the duration of a pulse of the second train. The most difficult problem in this type of system is the fact that the pulses do not always have sufficient time, which makes the "Time overlap" significant random enough.

For example, there may be mentioned a system for reading information transcribed in CMC7 code using a magnetizable ink. Such a system has been widely described in EP-A which was published on 30 April In short, remember that when a document eg a check carries information encoded by separate magnetized CMC7 sticks from each other by long intervals and short intervals, this reading is performed from a double magnetic head with two magnetoresistors separated by a predetermined distance.

As the information is represented by the number and order of succession of short and long intervals, analyzes the "temporal overlap" pulses from two separate pulse trains generated from the two magnetoresistors for detecting the passage of a long interval or a short interval before the double magnetic head during the reading of relative movement between this head and the document.

Therefore, it is understood that identification errors can occur if one of the pulses or both has too low accidentally duration to ensure the "temporal overlap" cited above which determines the detection of a rising or falling edge. Or, a given pulse from one or the other of the field plates may have a very short duration because it depends on the analog-digital conversion method used. This conversion is in fact made of a threshold switching circuit connected between each magnetoresistor and the rest of the system.

The principle and operation of such a threshold switching circuit are extensively described in EP-A However it will be recalled that for a given threshold, the pulses produced by the threshold detection circuit are all shorter than the amplitude of the analog signal is low. Conversely, for the same analog signal level, the greater the threshold is high more the resulting pulses are brief.

Finally, it must not lose sight of the fact that more than the threshold is low over the corresponding switching circuit is responsive to a hash such as the presence of magnetizable ink stains on the document, etc It is recalled that in the case of CMC7 code read by magnetoresistance, significant alternations of the analog signal are those which correspond to the single central alternating each response individuelle.

EA and EB inputs are connected respectively to two analog signal sources constituted here by two magnetoresistors A and B provided with their supply means in direct current, not shown separated by a certain distance and arranged in a system for creating a relative movement between these two magnetoresistors and a document especially a check carrying coded information CMC7, by a magnetized ink.

Thus, in the case of application to the character reading system encoded CMC7 the two processing channels are arranged to apply the rule identification of two types of intervals, referred to above. The device of the invention comprises four threshold switching circuits which two are set to a low threshold and two are set to a high threshold.

Each input is connected to two threshold switching circuits respectively set on a high threshold and a low threshold.

Thus, the EA input of the device is connected to the inputs of. SAb two switching circuits low threshold and SAh high threshold. The BA and BB-flops that are represented in the diagram of Figure 1 are of the kind which is commonly referred to as flip-named "dual-JK".

In the example described, these flip-flops, which are produced according to the well known TTL technology, are the type of those sold under the reference SN 74 LS by the American company called "Texas Instrument Corp. It is useful to mention here that the device structure shown in Figure 1 is such that, during operation, the conditions leading to an unstable state of the latch are never realized. In addition, said first gates NA1, NB1 of each combinational circuit have each two inputs, the first 1 is connected to the output of the switch circuit corresponding to low threshold that is to say, SAb, SBb, respectively and the second 2 input is connected to the other output of the device, that is to say one that does not correspond to the flip-flop controlled by the logic circuit to which belongs the NAND gate.

In the example shown, there is a NAND gate, but the combinational circuits could be designed equivalently either with simple gates, associated with circuits each connected inverters to the output of a gate And, either with oR gates associated with inverters connected circuits each on one of two inputs of each oR gate, in order to achieve at least the logical products SAb.

SB et SBb. SB and SBb. The output of the gate NA 1 which also constitutes an output of the com- bindtoire AC circuit is connected to the first input forcing S BA-flop and the output of the gate NB1 is connected to the first set input S the latch BB.

The gates NA2 and NB2 also each two inputs, a first input of the NA2 gate being connected to the output of SAb switching circuit and a first input of the NB2 gate being connected to the output of SBb switching circuit. The second input of the gate NA2 and NB2 second input of the gate are both connected to a reset source of reset pulses, these pulses corresponding for example to a readout period of document. In the example described, the reset source is set for permanently applying a logic 1 on the second inputs of the gates NA2 and NB2, except however for the brief moments when a reset is performed.

As apparent from the R and S reference letters used in accordance with the normalization for designating inputs BA and BB-flops, the first abovementioned forcing inputs are obviously set inputs while the second aforementioned forcing inputs are reset inputs to zero.

In Figure 2, there is shown a timing diagram illustrating the operation of part of the Figure 1 device whose function is to treat the pseudoperiodic analog signal generated by the magneto-A, that is to say the set-sous comprising the two switching circuits and SAb SAh, CA combinational circuit and flip-flop BA.

For each significant alternation of the pseudoperiodic signal generated by the magneto-A, BSA and SAh circuits generate two pulses with steep edges respective, shown in Figure 2. As mentioned above, these pulses are generated by switching between two voltage levels, which switching are controlled by the sign of the difference between the instantaneous value of the analog signal and the threshold low or high predetermined. It thus generates two separate sets of pulses from the same analog signal from the magnetoresistance A.

As is clear evidence of the operation with a threshold switching circuit described above, each pulse of the series associated with the low threshold SAb Figure 2 before I began appearance of analog pulse SAh in the series associated with the high threshold and persists after the disappearance of the latter.

From these two pulses, two cases are respectively shown possible by the left and right parts of the timing diagram of FIG 2. Second case: if the pulse transmitted to the output SB is not present at the time of the appearance of the leading edge of the pulse from the SAb circuit, the pulse generated at the output SA starts along the front before the pulse from the circuit SAh and ends along the back edge pulse, after the SAb circuit.

However, if the rocker BA is not triggered by the SAb condition. SB, it will be a little later by the leading edge of the pulse from the SAh circuit which is applied to the clock input H of the flip-flop BA. It should be noted that the pulse following the SB-flop and which is shown in the timing diagram of Figure 2 is itself a pulse having undergone the same treatment through SBb switching circuits, SBH, the combinational circuit CB and BB latch.

Of course, the invention is not limited to the embodiment just described, it includes all the technical equivalents of the means set if they are within the claims that follow. Method according to claim 1, characterised in that each pulse on the channel is generated whilst storing a voltage level during the aforesaid period of time. Method and apparatus for elaborating and processing two distinct pulse trains carrying information.

USA en. EPB1 en. JPSA en. BRA en. DED1 en. ESA1 en. FRB1 en. EPA1 en. ESA0 en. ESD0 en. FRA1 en. JPB2 en. TWIB en. CAA en. Asynchronous sampling digital detector system for magnetic and optical recording channels.

CHA5 en. Method and device for reading an information carrier of a codec according to a bar code. USB1 en. GBA en. Apparatus for detecting the absence of signal transitions from bit cells of a serial binary signal. Optical information carrier, optical device for generating tracking signals and optical device for generating error signals for focussing.

Method and device for detecting a transition of the DC component of a periodic signal, in particular for telephone junctor. EPA3 en. EPA2 en. TWA en. Method of and optical device for focusing a light beam onto a reference plane of an information carrier. Movement detector for systems for reducing noise visibility in television pictures.

Ref country code : GB Payment date : Year of fee payment : Ref country code : NL Payment date : Year of fee payment : Ref country code : DE Payment date : Year of fee payment : Lapsed in a contracting state announced via postgrant inform. Ref country code : GB Effective date : Ref country code : NL Effective date : Ref country code : DE Effective date :


Série d'exercices N°3-3tech-Bascules-Compteurs-2012-2013-Correction



Circuit intégré 4017



TD Bascules+Compteursl+Correction



TD3 VHDL Compteurs et registres


Related Articles