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D-Type Transparent. May General Description. These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relative- ly low-impedance loads The high-impedance state and in- creased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for inter- face or pull-up components They are particularly attractive for implementing buffer registers I O ports bidirectional bus drivers and working registers Continued.
Full parallel-access for loading. Buffered control inputs. P-N-P inputs reduce D-C loading on data lines. Connection Diagrams. Dual-In-Line Packages.
TL F —1. TL F —2. C National Semiconductor Corporation. TL F General Description Continued. The eight latches of the DM54 74LS are transparent D- type latches meaning that while the enable G is high the Q outputs will follow the data D inputs When the enable is taken low the output will be latched at the level of the data that was set up. The eight flip-flops of the DM54 74LS are edge-trig- gered D-type flip flops On the positive transition of the clock the Q outputs will be set to the logic states that were set up at the D inputs.
Function Tables. DM54 74LS A buffered output control input can be used to place the. The output control does not affect the internal operation of. LXQ 0. Logic Diagrams. Transparent Latches. TL F —3. Positive-Edge-Triggered Flip-Flops. TL F —4. Absolute Maximum Ratings See Note. If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications.
Supply Voltage. Input Voltage. Storage Temperature Range. Operating Free Air Temperature Range. Recommended Operating Conditions. High Level Input Votage. Low Level Input Voltage. High Level Output Current. Low Level Output Current. Pulse Width. Enable High. Note 2. Enable Low. Data Setup Time Notes 1 2. Data Hold Time Notes 1 2. Free Air Operating Temperature. Note 1. Input Clamp Voltage.
High Level Output Voltage. Low Level Output Voltage. Input Current Max Input Voltage. High Level Input Current. Low Level Input Current. I OZH. I OZL. Short Circuit. Output Current. Supply Current. Output Control to Any Q. Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second.
High Level Input Voltage. Clock High. Note 4. Clock Low. Data Setup Time Notes 1 4. Data Hold Time Notes 1 4. Maximum Clock Frequency. Physical Dimensions inches millimeters. Physical Dimensions inches millimeters Continued. National Semiconductor. Hong Kong Ltd. Japan Ltd. Fax a 49 85 Fax Arlington TX Email cnjwge tevm2 nsc com. Ocean Centre 5 Canton Rd. Tel 1 Fax 1 Tel a 49 85 85 Tel a 49 78 Tsimshatsui Kowloon Hong Kong.
Fran ais Tel a 49 93 Tel Tel a 49 16 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Learn more about Scribd Membership Home. Much more than documents. Discover everything Scribd has to offer, including books and audiobooks from major publishers. Start Free Trial Cancel anytime. Uploaded by api Document Information click to expand document information Date uploaded Oct 14, Did you find this document useful?
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74LS373 FLIP-FLOP. Datasheet pdf. Equivalent
Frank Donald October 27, 2 Comments. IC Working. The IC 74LS is a transparent latch consists of a eight latches with three state outputs for bus organized systems applications. As we all know the operation of flip flop that any input to the D pin at the present state will be given as output in next clock cycle. But when the Latch Enable Pin was pulled low, the data will be latched so that the data appears instantaneously providing a Latching action.
74LS373 Flip-Flops. Datasheet pdf. Equivalent